The present invention relates generally to device packaging, and more particularly to the device interconnections for mounting semiconductor devices to substrates.
Rapid advances in technology have accelerated the need for device interconnections which can satisfy, among other requirements, a greater number of functions and increased speed without compromising yield or reliability. Conventional device interconnections include ball grid arrays, wire bonding, tape automated bonding, and controlled collapse chip connections, such as flip chip packages. Flip chip packages tend to be particularly popular because they have higher densities, thereby allowing more functions to be incorporated in a single package.
Conventional packaging techniques, including flip chip packages, however, fail to address the specific needs of high frequency semiconductor devices, particularly with respect to providing low loss, reproducible electrical interconnections at the substrate level for mounting semiconductors. Specifically, the attachment material in flip chip packages, typically solder, epoxy or gold, is applied directly to a semiconductor which is then aligned and attached to a substrate. Flip chip packaging techniques which utilize solder-type bump attachments are limited due to non-uniformity of solder bumps, poor wetting quality and reduced reliability caused by the use of fluxes. Additionally, because of the toxic nature of lead, elaborate manufacturing facilities are needed, resulting in high production costs and poor thermal conductivity particularly with respect to lead/tin based solder.
Flip chip packages which utilize epoxy-type bump attachments suffer from problems as well, including non-uniformity of epoxy bumps, a need for special application equipment, epoxy outgassing, bleed out contamination, poor thermal conductivity and restrictions in applying opto-electronic devices. Similarly, some of the problems associated with flip chip packages utilizing gold-type bumps include non-uniformity of gold bumps, poor thermal conductivity and size restrictions, with each ball typically having a minimum diameter of 125 microns.
What is needed therefore is a low loss, economical device interconnection for connecting semiconductors to substrates which would provide high bandwidth connections and provide improvements in yield and reliability.